Storage Temperature

TS

-40

85

°C

Supply Voltage

VCC

-0.5

3.6

V

Relative Humidity (non-condensing)

RH

5

95

%

Non-condensing

Data Input Voltage Differential

lV_DIP-V_DINl

-

1

V

Control Input Voltage

VI

-0.3

V_CC+0.5

V

Control Output Voltage

VI

-20

20

V

Operating Case Temperature

T_OPR

0

-

70

°C

Power Supply Voltage

V_CC

3.135

3.3

3.465

V

Instantaneous Peak Current at Hot Plug

I_{CC_IP}

-

-

4800

mA

Sustained Peak Current at Hot Plug

I_{CC_SP}

-

-

3960

mA

Maximum Power Dissipation

P_D

-

-

12

W

Maximum Power Dissipation, Low Power Mode

P_DLP

-

-

1.5

W

Signaling Rate per Lane

SRL

-

53.125

-

GBd

1

Two Wire Serial Interface Clock Rate

-

-

-

400

kHz

Power Supply Noise Tolerance

-

-

-

66

mV

2

Rx Differential Data Output Load

-

-

100

-

Ω

Operating Distance

-

2

-

2000

m

Receiver (Module Output)

AC Common-Mode Output Voltage (RMS)

-

-

17.5

mV

Differential Output Voltage

-

-

900

mV

Near-End Eye Height, Differential

70

-

-

mV

Far-End Eye Height, Differential

30

-

-

mV

Far End Pre-Cursor Ratio

-4.5

-

2.5

%

Differential Termination Mismatch

-

-

10

%

Transition Time (Min., 20% To 80%)

9.5

-

-

ps

DC Common Mode Voltage

-350

-

2850

mV

Transmitter (Module Input)

Differential pk-pk Input Voltage Tolerance

900

-

-

mV

Differential Termination Mismatch

-

-

10

%

Single-Ended Voltage Tolerance Range

-0.4

-

3.3

V

DC Common Mode Voltage

-350

-

2850

mV

Module Output SCL and SDA

V_OL

0

0.4

V

Module Input SCL and SDA

V_IL

-0.3

V_CC*0.3

V

V_IH

V_CC*0.7

V_CC+0.5

V

InitMode, ResetL, and ModSelL

V_IL

-0.3

0.8

V

V_IH

2

V_CC+0.3

V

IntL

V_OL

0

0.4

V

V_OH

V_CC-0.5

V_CC+0.3

V

Transmitter

Wavelength L0

λ_C0

1264.5

1271

1277.5

nm

Wavelength L1

λ_C1

1284.5

1291

1297.5

nm

Wavelength L2

λ_C2

1304.5

1311

1317.5

nm

Wavelength L3

λ_C3

1324.5

1331

1337.5

nm

Side Mode Suppression Ratio

SMSR

30

-

-

dB

Average Launch Power, each Lane

AOPL

-3.3

-

3.5

dBm

1

Outer Optical Modulation Amplitude (OMA_outer), each Lane

T_OMA

-0.3

-

3.7

dBm

2

Difference in Launch Power between any Two Lanes (OMA_outer)

DP

-

-

4

dB

Launch Power in OMA_outer Minus TDECQ for ER ≥ 4.5 dB, each Lane

T_OMA-TDECQ

-1.7

-

-

dBm

Launch Power in OMA_outer Minus TDECQ for ER<4.5 dB, each Lane

T_OMA-TDECQ

-1.6

-

-

Transmitter and Dispersion Eye Closure for PAM4 (TDECQ), each Lane

TDECQ

-

-

3.4

dB

TDECQ - 10*log10(Ceq), each Lane

-

-

3.4

dB

Average Launch Power of OFF Transmitter, each Lane

T_OFF

-

-

-20

dBm

Extinction Ratio, each lane

ER

3.5

-

-

dB

Transmitter Transition Time

TT

-

-

17

ps

RIN_17.1OMA

RIN

-

-

-136

dB/Hz

Optical Return Loss Tolerance

ORL

-

-

17.1

dB

Transmitter Reflectance

T_R

-

-

-26

dB

3

Receiver

Wavelength L0

λ_C0

1264.5

1271

1277.5

nm

Wavelength L1

λ_C1

1284.5

1291

1297.5

nm

Wavelength L2

λ_C2

1304.5

1311

1317.5

nm

Wavelength L3

λ_C3

1324.5

1331

1337.5

nm

Damage Threshold, each Lane

AOP_D

4.5

-

-

dBm

Average Receive Power, each Lane

AOP_R

-7.3

-

3.5

dBm

4

Receive Power (OMA_outer), each Lane

OMA_R

-

-

3.7

dBm

Difference in Receive Power between any Two Lanes

(Oma_outer)

DR

-

-

4.1

dB

Receiver Reflectance

RR

-

-

-26

dB

Receiver Sensitivity (OMA_outer), each lane

S_OMA

-

-

Max(-4.6,

SECQ-6)

dBm

5

Stressed Receiver Sensitivity (OMA_outer), each lane

SRS

-

-

-2.6

dBm

6

Conditions of Stressed Receiver Sensitivity Test

Stressed Eye Closure for PAM4 (SECQ)

-

-

3.4

-

dB

SECQ - 10*log10(Ceq), Lane under Test (Max.)

-

-

-

3.4

dB

OMA_outer of each Aggressor Lane

-

-

1.5

-

dBm

MgmtInit Duration

-

2000

ms

ResetL Assert Time

t_reset_init

10

-

µs

IntL Assert Time

ton_IntL

-

200

ms

IntL Deassert Time

toff_IntL

-

500

µs

Rx LOS Assert Time

ton_los

-

100

ms

Rx LOS Assert Time (fast mode)

ton_losf

-

1

ms

Tx Fault Assert Time

ton_Txfault

-

200

ms

Flag Assert Time

ton_flag

-

200

ms

Mask Assert Time

ton_mask

-

100

ms

Mask Deassert Time

toff_mask

-

100

ms

Rx Squelch Assert Time

ton_Rxsq

-

500

ms

Rx Squelch Deassert Time

toff_Rxsq

-

15

s

Tx Squelch Assert Time

ton_Txsq

-

400

ms

Tx Squelch Deassert Time

toff_Txsq

-

5

s

Tx Disable Assert Time

ton_Txdis

-

100

ms

Tx Disable Assert Time (fast mode)

ton_Txdisf

-

3

ms

Tx Disable Deassert Time

toff_Txdis

-

400

ms

Tx Disable Deassert Time (fast mode)

toff_Txdisf

-

10

ms

Rx Output Disable Assert Time

ton_Rxdis

-

100

ms

Rx Output Disable Deassert Time

toff_Rxdis

-

100

ms

Squelch Disable Assert Time

ton_sqdis

-

NA

ms

Not supported

Squelch Disable Deassert Time

toff_sqdis

-

NA

ms

Not supported

Temperature

0 to 70

±3

°C

Internal

Voltage

0 to VCC

3%

V

Internal

Tx Bias Current (each Lane)

0 to 100

10%

mA

Internal

Tx Output Power (each Lane)

-3.3 to +3.5

±3

dB

Internal

Rx Receive Power (each Lane)

-7.3 to +3.5

±3

dB

Internal