
Ascent’s QSFP+ transceiver modules are designed for use in 40 Gigabit per second links over multimode fiber. They are compliant with the SFF-8436 and IEEE 802.3 40GBASE-SR4. Digital diagnostics functions are available via a I²C interface, including Tx and Rx power monitoring. The optical transceiver is compliant per the RoHS Directive 2011/65/EU. The optical transmitter portion of the transceiver incorporates a 4-channel VCSEL array, a 4-channel input buffer and laser driver, diagnostic monitors, control and bias blocks. For module control, the control interface incorporates a Two Wire Serial interface of clock and data signals. Diagnostic monitors for VCSEL bias, module temperature, transmitted optical power, received optical power and supply voltage are implemented and results are available through the TWS interface. Alarm and warning thresholds are established for the monitored attributes. Fault detection or channel deactivation through the TWS interface will disable the channel. Status, alarm/warning and fault information are available via the TWS interface. The optical receiver portion of the transceiver incorporates a 4-channel PIN photodiode array, a 4- channel TIA array, a 4-channel output buffer, diagnostic monitors, and control and bias blocks. Diagnostic monitors for optical input power are implemented and results are available through the TWS interface. Alarm and warning thresholds are established for the monitored attributes.
· Compliant with SFF-8436
· Compliant with IEEE 802.3 40GBASE-SR4
· 850nm 4 VCSEL Lasers and 4 channels PIN photo detectors
· Maximum link length of 100m on OM3 MMF or 150m on OM4 MMF
· 3.3V Supply Voltage
· Max. Power<1.5W
· 0-70°C Case Operating Temperature
· MPO Receptacle
· Maximum Data Rate per Lane: 10.3125Gb/s
· 2-wire interface for management and DDM
· Complies with EU Directive 2011/65/EU
· Class 1 Laser
Parameter | Symbol | Min | Typ. | Max | Unit | Note |
Storage Temperature | Ts | -40 | - | +85 | °C | |
Relative Humidity (non-condensing) | RH | 5 | - | 95 | % | |
Supply Voltage | Vcc | -0.5 | - | 3.6 | V | |
Input Voltage | Vin | -0.5 | - | Vcc+0.5 | V |
Recommended Operating Conditions
Parameter | Symbol | Min | Typ. | Max | Unit | Note |
Operating Case Temperature | TOPR | 0 | - | 70 | °C | |
Power Supply Voltage | Vcc | 3.135 | 3.3 | 3.465 | V | |
Power Supply Current | Icc | 475 | mA | |||
Maximum Power Consumption | P_D | - | - | 1.5 | W | |
Data Rate per Lane | DR | - | 10.3125 | - | Gb/s | |
Operating Distance (MMF OM3) | - | 0.5 | - | 100 | m | |
Operating Distance (MMF OM5) | - | 0.5 | - | 150 | m |
Parameter | Symbol | Min | Typ. | Max | Unit | Note |
Transmitter | ||||||
Mean Wavelength (Each Lane) | λ | 840 | 850 | 860 | nm | |
Data Rate per Lane | DR | 10.3125 | Gbps | |||
Spectral Width (RMS) | Δλ | 0.65 | nm | |||
Optical Power (Each Lane) | POUT | -7.6 | - | 2.4 | dBm | |
OMA per Lane | Poma | -5.6 | 3 | dBm | ||
Peak Power, each Lane | P_peak | 4 | dBm | |||
Extinction Ratio | ER | 3 | dB | |||
TDP, each Lane | TDP | 3.5 | dB | |||
Optical Return Loss Tolerance | 12 | dB | ||||
Average Launch Power Tx_Off(Each Lane) | -30 | dBm | ||||
Receiver | ||||||
Wavelength(Each Lane) | λ | 840 | 850 | 860 | nm | |
Data rate per Lane | DR | 10.3125 | Gbps | |||
Average Power at Receiver, each Lane | - | -9.5 | - | 2.4 | dBm | |
Rx OMA per Lane | OMA | - | - | 3 | dBm | |
Stressed Receiver Sensitivity OMA (Each Lane) | SRS | - | - | -5.4 | dBm | |
Peak Power(Each lane) | - | - | - | 4 | dBm | |
Receiver Reflectance | RX_R | - | - | -12 | dB | |
LOS Assert | LOS_A | -30 | - | - | dBm | |
LOS De-Assert | LOS_D | - | - | -12 | dBm | |
LOS Hysteresis | - | 0.5 | - | dB | ||
Parameter | Symbol | Min | Typ. | Max | Unit | Note |
Supply Voltage | Vcc | 3.135 | 3.465 | V | ||
Supply Current | Icc | 450 | mA | |||
Input Differential Impedance | 90 | 100 | 110 | Ω | ||
Differential Data Input Swing | VIN, P-P | 300 | - | 1100 | mVpp | |
Differential Data Output Swing | Vout, P-P | 300 | 850 | mVpp | ||
Input Logic Level High | 2 | Vcc | ||||
Input Logic Level Low | 0 | 0.8 | ||||
Output Logic Level High | Vcc-0.5 | Vcc | ||||
Output Logic Level Low | 0 | 0.4 |
Parameter | Symbol | Min | Typ. | Max | Unit | Note |
Host 2-Wire Vcc Voltage | Vcc_Host_2w | 3.14 | - | 3.46 | V | |
SCL and SDA Voltage | V_OL | 0 | - | 0.4 | V | |
V_OH | Vcc_Host_2w-0.5 | - | Vcc_Host_2w+0.3 | V | ||
V_IL | -0.3 | - | VccT*0.3 | V | ||
V_IH | VccT*0.7 | - | VccT+0.5 | V | ||
Input Current on the SCL and SDA Contacts | Ii | -10 | - | 10 | mA |
Parameter | Symbol | Min | Typ. | Max | Unit | Note |
Transmitter | ||||||
Clock Frequency | f_scl | 100 | 400 | kHZ | 1 | |
Clock Pulse Width Low | t_low | 1.3 | - | µs | ||
Clock Pulse Width High | t_high | 0.6 | - | µs | ||
Time Bus Free before New Transmission Can Start | t_buf | 20 | - | µs | 2 | |
START Hold Time | t_HD,STA | 0.6 | 0 | µs | ||
START Set-up Time | t_SU,STA | 0.6 | - | µs | ||
Data In Hold Time | t_HD,DAT | 0 | - | µs | ||
Data In Set-up Time | t_SU,DAT | 0.1 | - | µs | ||
Input Rise Time(100kHz) | tr,100 | - | 1000 | ns | 3 | |
Input Rise Time(400kHz) | tr,100 | - | 300 | ns | 3 | |
Input Fall Time(100kHz) | tf,100 | - | 300 | ns | 4 | |
Input Fall Time(400kHz) | tf,400 | - | 300 | ns | 4 | |
STOP Set-up Time | t_SU,STO | 0.6 | - | us | ||
1. Module shall operate with fSCL up to 100 kHz without requiring clock stretching. The module may clock stretch with fSCL greater than 100 kHz and up to 400 kHz.
2. Between STOP and START and between ACK and ReSTART.
3. From (VIL,MAX-0.15) to (VIH,MIN+0.15).
4. From (VIH,MIN+0.15) to (VIL,MAX-0.15).
Parameter | Symbol | Min | Typ. | Max | Unit | Note |
Serial Interface Clock Holdoff “Clock Stretching” | T_clock_hold | 500 | µs | 1 | ||
Complete Single or Sequential Write up to 4 Byte | tWR | 40 | ms | |||
Complete Sequential Write of 5 to 8 Byte | tWR | 80 | ms | |||
Endurance (Write Cycles) | 10K | - | - | ms |


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