·         Compliant to 100G Lambda MSA 100G LR1-10

·         Full-duplex transceiver module

·         1x106.25Gb/s(PAM4) optical interface

·         2x53.125Gb/s(PAM4) electrical interface

·         106.25Gbps PAM4 based on a cooled EML TOSA transmitter

·         106.25Gbps PAM4 PIN Receiver

·         3.5W maximum power consumption

·         Hot-pluggable SFP56-DD form factor

·         Maximum link length of 10km on G.652 SMF with KP-FEC

·         Duplex LC receptacles

·         Built-in digital diagnostic functions

·         Operating case temperature range: 0 to 70°C

·         Single 3.3V power supply

·         RoHS compliant (lead free)

Absolute Maximum Ratings

Recommended Operating Conditions

Electrical Characteristics

Notes:
    1.       Differential input voltage amplitude is measured between TxnP and TxnN.
    2.       Differential output voltage amplitude is measured between RxnP and RxnN.

Optical Characteristics

The Lower Memory Overview

Page 00h Memory Overview

Page 01h Memory Overview

    3.     Due to eight-bit addresses, This limits the management memory that can be directly accessed by the host to 256 bytes, which is divided in Lower Memory (addresses 00h through 7Fh) and Upper Memory (addresses 80h through FFh).
    4.     The addressing structure of the additional internal management memory1 is shown in below figure.
            The management memory inside the module is arranged as a unique and always host accessible address space of 128 bytes (Lower Memory) and as multiple upper address subspaces of 128 bytes each (Pages),
            only one of which is selected as host visible in Upper Memory. A second level of Page selection is possible for Pages for which several instances exist (e.g. where a bank of pages with the same Page number exists).

Page 13h Memory Overview

Page 14h Memory Overview

     5.    This structure supports a flat 256 byte memory for passive copper modules and permits timely access to addresses in the Lower Memory, e.g. Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page 
              Select function in the Lower Page. For more complex modules which require a larger amount of management memory the host needs to use dynamic mapping of the various Pages into the host addressable Upper Memory address space, whenever needed.
       6.   The management memory map has been designed largely after the CMIS memory map where pages and banks are used in order to enable time critical interactions between host and module while expanding the memory size. This memory map has been changed in
              order to accommodate just two electrical lanes and to limit the required memory. The single address approach is used as found in QSFP.

Regulatory Compliance
Ascent’s SFP56-DD-LR10 transceivers are Class 1 Laser Products. They meet the requirements of the following standards.